An open drain bus, such as an Inter-Integrated Circuit (I2C) bus, a System Management Bus (SMBus), and others, usually includes a data line and a clock line. Such a data line and a clock line can each be referred to individually as a bus line, or simply as a line. As shown in FIG. 1a, each bus line (e.g., 101) is connected to a pull-up resistor R, pull down transistors Q1, Q2 and Q3 (each associated with an interface device) and a capacitance C. The capacitance C represents distributed capacitance of the bus line and the total input capacitance of interface devices 111, 112 and 113. Data transfer rate depends on how fast the resistor R can charge the capacitance C. To increase the maximum data transfer rate, a bus line 101 can be separated into segments (e.g., 101A, 101B and 101C), each having a reduced capacitance, as shown in FIG. 1b. FIG. 1b also shows that bi-directional buffers 102 can be used to transfer data between these segments. Existing bi-directional buffers are often susceptible to latch-up when the buffers are in a low logic state. To attempt to combat such latch-up, some buffers have introduced an input offset. However, such an input offset increases the input-to-output offset, which is undesirable. Accordingly, there is still a need for new bi-directional buffers that overcome at least some, and preferably all, of the deficiencies of existing bi-directional buffers.